The invention relates to a circuit for correction of deflection errors in a television display and in particular to the correction of the vertical convergence in a projection television display.
Circuits of this type are used for correction of parameters in a raster deflection, for example for correction of north/south and east/west distortion, pin-cushion distortion, nonlinearity in the deflection, and other geometric and convergence errors in the horizontal and vertical directions. One particular field of application is convergence correction in a projection television set, in which the pictures from three monochrome tubes arranged alongside one another are projected onto a screen, where they are superimposed to be coincident. The term television set in this context means any equipment with an electronic raster picture display. The equipment may be fed from a television broadcast signal or else, as a pure monitor, from an RGB signal, a composite video signal, or separately with luminance and color sub-carrier signals (YC) from any desired video signal source.
For example in the case of convergence correction in a projection television set, the deflection parameters are corrected by means of correction values which are stored as digital signals in a memory for the correction and are called up successively in time during the deflection process, and are converted via a D/A converter into an analogue signal forming a correction current by means of a correction coil.
The deflection errors, in particular the convergence errors in such a projection set, are in each case at their greatest at the corners of the picture and at the upper and lower edges of the picture, so that, as a rule, the correction current also assumes its maximum value at these points. The peak value of the correction current at the upper and lower picture edges may, for example, be approximately 1.5 amperes for the vertical convergence correction values. Such high currents result in a significant power loss, in the order of magnitude of approximately 5 watts/channel in the driver circuits, the output amplifiers, in the resistance loss of the correction coil and, possibly, in negative feedback resistors or current measurement resistors connected in series with the coil.
The invention reduces power losses in such a correction circuit without any adverse effect on the correction itself.
In the case of the invention, the correction current is thus reduced considerably, in particular being set to zero, during the vertical flyback period or during a time window in which no visible picture is displayed. The invention is in this case based on the following knowledge and considerations: the correction current, which generally has its maximum value at the end of the forward-sweep time, has until now continued at this maximum value during the flyback time, or has changed its mathematical sign during the flyback time. This results in a time window, in which no picture is displayed, between two forward-sweep times during which a visible picture is displayed. In consequence, no convergence correction is required during this time window since, during this time, geometric errors such as convergence errors cannot be seen in the displayed picture. The correction current is advantageously switched off during this time, without this having any adverse effect on the displayed picture. The advantage is a considerable power saving, of approximately 4 watts/channel. The reduced overall power losses also allow simpler driver circuits and output stages with simpler transistors to be implemented. Thus, overall, the invention reduces the production and operating costs of such a correction circuit considerably, without the geometric correction in the visible picture being adversely effected in the process.
The correction current is preferably set to zero during the time window. It is also conceivable for the correction current to be reduced only to a considerably lower level, and even this likewise allows a considerable power saving. The correction signal is taken from a memory and advantageously controlled at the input of a D/A converter to produce the advantageous reduction in correction current. The DIA converter converts the digital correction signal into an analogue signal forming the correction current.
One embodiment of the invention takes account of an offset which is an undesirable and unavoidable signal change or signal shift in the analogue part of the circuit by, for example offset voltages. It is assumed that the digital zero value of the digital signal is a value which produces a correction current with the value zero without any such offset error. When an offset error is present, this digital zero value then produces a correction current which is not zero. To compensate for this discrepancy, a correction is thus introduced into the digital signal. In contrast to the digital zero value, the digital value is changed to a corrected digital zero value, in which the analogue correction current that is initiated actually assumes the value zero, despite the offset error. Details of such an offset correction are described in DE 42 14 317.9, which corresponds to U.S. Pat. No. 5,488,271.
In practice, parts of lines which are located outside the visible picture area may partially intrude into the visible part of the picture owing to geometric distortion in the form of bending, unless they are corrected. Therefore, according to one embodiment of the invention, the duration and the timing of the time window with the reduction of the correction current are chosen such that the lines at the upper and lower picture edges, which would partially intrude into the visible part of the picture owing to bending if there were no correction, are located outside the time window. This ensures that the lines outside the visible picture which would interfere with the visible picture if the correction current were switched off are still subject to correction.